author | Huang Haibin <haibin.huang@intel.com> | |
Wed, 17 Oct 2018 02:55:13 +0000 (10:55 +0800) | ||
committer | Huang Haibin <haibin.huang@intel.com> | |
Wed, 17 Oct 2018 02:55:13 +0000 (10:55 +0800) | ||
commit | 1e1a8bfbc608f7f144c7fbdfc7e7bb1281dd149e | |
tree | 42014074e69bc67d0442986282d9810b6242f0ab | tree | snapshot |
parent | 944c2365050ddabd80a63c2da730c489482115cd | commit | diff |
tosca/vCPE/README.md | diff | blob | history | |
tosca/vCPE/generate_csar.sh | diff | blob | history | |
tosca/vCPE/infra/MainServiceTemplate_sriov.yaml | [new file with mode: 0644] | blob |
tosca/vCPE/vbng/MainServiceTemplate_sriov.yaml | [new file with mode: 0644] | blob |
tosca/vCPE/vbrgemu/MainServiceTemplate_sriov.yaml | [new file with mode: 0644] | blob |
tosca/vCPE/vgmux/MainServiceTemplate_sriov.yaml | [new file with mode: 0644] | blob |
tosca/vCPE/vgw/MainServiceTemplate_sriov.yaml | [new file with mode: 0644] | blob |